The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which is effective when applied to a testing technique in a semiconductor integrated circuit device such as a gate array having a RAM (i.e., Random Access Memory, as will be shortly referred to as the "RAM") packaged therein.
A conventional testing technique of a packaged RAM is disclosed in Japanese Patent Laid-Open No. 170100/1987, for example. This semiconductor integrated circuit device is equipped with a selector for preventing an increase in the number of diagnosis terminals, so that the output of the packaged RAM is selected by the selector and outputted from the LSI (or semiconductor integrated circuit device).